1. Field of the Invention
The present invention relates to integrated circuits, and more particularly, to a latchup prevention method for integrated circuits, and device using the same.
2. Description of the Related Art
Latchup effect is an important reliability issue in CMOS integrated circuit (IC), in which low impedance paths are formed by activation of a parasitic PNPN SCR (silicon controlled rectifier). Since the power supply has a low shunt impedance to ground during latchup, a large current occurs between the power supply and the ground. This results in logic errors or malfunctions of circuits, or even irreversible damage to the IC. Unfortunately, because the P+ region of PMOS and N-well, P-sub and N+ regions of NMOS in integrated circuitry form a PNPN SCR structure, the parasitic SCR is inherent in CMOS process.
There are many origins and causes of latchup in CMOS. However, the most prominent is substrate current produced by hot carrier effect and/or forward biasing of parasitic diodes by noise appear on the pad during chip operation. Most substrate current (Isub) that results in latchup is injected from parasitic diodes formed by ESD protection circuits, as shown in FIG. 1. Activation of the parasitic SCR is triggered by the parasitic PNP transistor (P+/N-well/P-sub) and the parasitic NPN transistor (N-well/P-sub/N+). Further, the two transistors are activated if the base-emitter voltage (Vbe) across the base-emitter junction exceeds 0.7V. This voltage builds up according to the IR drop on the well/substrate resistor, such that well/substrate resistance or bipolar gain of parasitic transistors must be reduced in order to prevent latchup.
Conventional solutions for latchup and drawbacks thereof follow.
First, latchup can be prevented by process technique. Epitaxial CMOS can provide well/substrate resistance, and trench isolation and silicon on insulator (SOI) can minimize coupling between parasitic PNP and NPN transistors. Thus, epitaxial CMOS, trench isolation and silicon on insulator (SOI) can provide latchup prevention. However, this increases process complexity and fabrication costs.
Further, latchup can also be prevented during layout. Majority and minority-carrier guard rings are thereby commonly used, decoupling parasitic bipolar transistors and collecting injected carriers before latchup in CMOS internal circuit is induced by the injected carriers. Well/substrate resistance is reduced by increasing pickup contact in well and substrate and/or by reducing distance between the device diffusion area and pickup contacts, thereby increasing latchup resistance. However, such solution requires large layout area and increases chip size, with utilization limited by specific layout restrictions. While an alternative is to increase the distance between the I/O injector and internal circuit, this increases total chip size dramatically and is frequently limited in use.
Moreover, latchup can also be prevented with circuit techniques. A latchup detection circuit is disclosed by Shen et al. in U.S. Pat. No. 5,942,932, in which changes in well/substrate voltage potential are detected and activate the circuit during latchup to pull back the well/substrate voltage potential to the original value thereof. This, however, also increases circuit complexity and layout space requirements.
Therefore, there is a need for a method to avoid latchup in integrated circuits under conditions in which restricted layout area precludes deployment of guard rings and well/substrate pickup contacts near the internal circuits.